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RFM42B/43B
RFM42B/43B ISM TRANSMITTER
Features
V1.0
Frequency range 433/868/915MHz ISM bands

Output Power Range +1 to +20dBm (RFM42B) -8 to +13dBm (RFM43B) Low Power Consumption
RFM42B
85 mA @ +20 dBm
RFM43B

30 mA @ +13 dBm Data Rate = 0.123 to 256 kbps FSK, GFSK, and OOK modulation Power Supply = 1.8 to 3.6 V

Ultra low power shutdown mode Wake-up timer Integrated 32 kHz RC or 32 kHz XTAL Integrated voltage regulators Configurable packet handler TX 64 byte FIFO Low battery detector Temperature sensor and 8-bit ADC -40 to +85 C temperature range Integrated voltage regulators Frequency hopping capability On-chip crystal tuning 14-PIN DIP & 16-PIN SMD package Low cost Power-on-reset (POR)
RFM42B/43B
Applications

Remote control Home security & alarm Telemetry Personal data logging Toy control Wireless PC peripherals

Remote meter reading Remote keyless entry Home automation Industrial control Sensor networks Health monitors
Description
HopeRF's RFM42B/43B are highly integrated, low cost,433/868/915MHZ wireless ISM transmitters module. The RFM42B/43B offers advanced radio features including adjustable power output levels of -8 to +13dBm on the RFM43B and +1 to +20dBm on the RFM42B.Power adjustments are made in 3dB steps.The RFM42B/43B's high level of integration offers reduced BOM cost while simplifying the overall system design. The RFM42B's Industry leading +20dBm output power ensures extended range and improved link performance. Additional system features such as an automatic wake-up timer, low battery detector, 64 byte TX FIFO, and automatic packet handling reduce overall current consumption and allow the use of lower-cost system MCUs. An integrated temperature sensor, general purpose ADC, power-on-reset (POR), and GPIOs further reduce overall system cost and size. The direct digital transmit modulation and automatic PA power ramping ensure precise transmit modulation and reduced spectral spreading ensuring compliance with global regulations including FCC,ETSI regulations. An easy-to-use calculator is provided to quickly configure the radio settings, simplifying customer's system design and reducing time to market.
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RFM42B/43B TABLE O F CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3. Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2. Operating Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4. System Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5. Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4. Modulation Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1. Modulation Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.2. Modulation Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5. Internal Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1. Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 5.2. Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.3. Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 5.4. Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 6. Data Handling and Packet Handler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.1. TX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.2. Packet Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.3. Packet Handler TX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.4. Data Whitening, Manchester Encoding, and CRC . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5. Synchronization Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.6. TX Retransmission and Auto TX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7. Auxiliary Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 7.1. Smart Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 7.2. Microcontroller Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 7.3. General Purpose ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4. Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 7.5. Low Battery Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 7.6. Wake-Up Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7. GPIO Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8. Reference Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9. Application Notes and Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10. Pin Descriptions: RFM42B/43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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RFM42B/43B
11. Mechanical Dimension: RFM42B/ 43B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12. Ordering Information: RFM42B/43B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 .. Contact Information: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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RFM42B/43B
1. Electrical Specifications
Table 1. DC Characteristics
Parameter
Supply Voltage Range Power Saving Modes
Symbol
VDD IShutdown IStandby ISleep ISensor-LBD ISensor-TS IReady
Conditions
Min
1.8
Typ
3.0 15 450 1 1 1 800 8.5 85 30
Max Units
3.6 50 800 -- -- -- -- -- -- -- V nA nA A A A A mA mA mA
RC Oscillator, Main Digital Regulator, and Low Power Digital Regulator OFF Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator, and RC Oscillator OFF RC Oscillator and Low Power Digital Regulator ON (Register values retained) and Main Digital Regulator OFF Main Digital Regulator and Low Battery Detector ON, Crystal Oscillator and all other blocks OFF Main Digital Regulator and Temperature Sensor ON, Crystal Oscillator and all other blocks OFF Crystal Oscillator and Main Digital Regulator ON, all other blocks OFF. Crystal Oscillator buffer disabled Synthesizer and regulators enabled txpow[2:0] = 111 (+20 dBm) txpow[2:0] = 111 (+13 dBm)
-- -- -- -- -- -- -- -- --
TUNE Mode Current TX Mode Current --RFM42B TX Mode Current --RFM43B
ITune ITX_+20 ITX_+13
ITX_+1
txpow[2:0] = 011 (+1 dBm)
--
18
--
mA
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RFM42B/43B
Table 2. Synthesizer AC Electrical Characteristics
Parameter Synthesizer Frequency Range--RFM42B/43B Synthesizer Frequency Resolution Reference Frequency Input Level Synthesizer Settling Time Symbol Conditions 433MHz band FSYN FRES-LB FRES-HB fREF_LV 868MHz band 915MHz band 433MHz Band 868/915MHz Band When using external reference signal driving XOUT pin, instead of using crystal. Measured peak-to-peak (VPP) Measured from exiting Ready mode with XOSC running to any frequency. Including VCO calibration. Integrated over 250 kHz bandwidth (500 Hz lower bound of integration) F = 10 kHz F = 100 kHz F = 1 MHz F = 10 MHz Min 413 848 901 -- -- 0.7 156.25 312.5 -- Typ Max 453 888 929 -- -- 1.6 Units MHz MHz MHz Hz Hz V
tLOCK
--
200
--
s
Residual FM Phase Noise
FRMS L(fM)
-- -- -- -- --
2 -80 -90 -115 -130
4 -- -- -- --
kHzRMS dBc/Hz dBc/Hz dBc/Hz dBc/Hz
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RFM42B/43B
Table 3. Transmitter AC Electrical Characteristics
Parameter TX Frequency Range--RFM42B/43B FSK Data Rate OOK Data Rate Modulation Deviation Modulation Deviation Resolution Output Power Range --RFM42B Output Power Range--RFM43B TX RF Output Steps TX RF Output Level Variation vs. Temperature TX RF Output Level Variation vs. Frequency Transmit Modulation Filtering Spurious Emissions Symbol Conditions 433MHz band FTX DRFSK DROOK f1 f2 fRES PTX PTX PRF_OUT PRF_TEMP PRF_FREQ B*T controlled by txpow[2:0] -40 to +85 C Measured across any one frequency band Gaussian Filtering Bandwith Time Product POUT = 13 dBm, Frequencies <1 GHz 868/915MHz band 433MHz band 868MHz band 915MHz band Min 413 848 901 0.123 0.123 0.625 0.625 -- +1 -8 -- -- -- -- 0.625 -- -- 3 2 1 0.5 -- -- Typ Max 453 888 929 256 40 320 160 -- +20 +13 -- -- -- -- Units MHz MHz MHz kbps kbps kHz kHz kHz dBm dBm dB dB dB
POB-TX1
--
--
-54
dBm
POB-TX2
1-12.75 GHz, excluding harmonics
--
--
-54
dBm
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RFM42B/43B
Table 4. Auxiliary Block Specifications
Parameter Temperature Sensor Accuracy Temperature Sensor Sensitivity Low Battery Detector Resolution Low Battery Detector Conversion Time Microcontroller Clock Output Frequency Symbol TSA TSS LBDRES LBDCT FMC Configurable to 30 MHz, 15 MHz, 10 MHz, 4 MHz, 3 MHz, 2 MHz, 1 MHz, or 32.768 kHz Conditions After calibrated via sensor offset register tvoffs[7:0] Min -- -- -- -- 32.768K Typ 0.5 5 50 250 -- Max -- -- -- -- 30M Units C mV/C mV s Hz
General Purpose ADC Resolution General Purpose ADC Bit Resolution Temp Sensor & General Purpose ADC Conversion Time 30 MHz XTAL Start-Up time
ADCENB ADCRES ADCCT
-- -- --
8 4 305
-- -- --
bit mV/bit s
t30M
--
600
--
s
30 MHz XTAL Cap Resolution 32 kHz XTAL Start-Up Time 32 kHz XTAL Accuracy using 32 kHz XTAL 32 kHz Accuracy using Internal RC Oscillator POR Reset Time Software Reset Time
30MRES t32k 32KRES 32KRCRES tPOR tsoft
-- -- -- -- -- --
97 6 100 2500 16 100
-- -- -- -- -- --
fF sec ppm ppm ms s
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RFM42B/43B
Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ)
Parameter Rise Time Fall Time Input Capacitance Logic High Level Input Voltage Logic Low Level Input Voltage Input Current Logic High Level Output Voltage Logic Low Level Output Voltage Symbol TRISE TFALL CIN VIH VIL IIN VOH VOL 0Table 6. GPIO Specifications (GPIO_0, GPIO_1, and GPIO_2)
Parameter Rise Time Fall Time Input Capacitance Logic High Level Input Voltage Logic Low Level Input Voltage Input Current Input Current If Pullup is Activated Maximum Output Current Symbol TRISE TFALL CIN VIH VIL IIN IINP IOmaxLL IOmaxLH IOmaxHL IOmaxHH Logic High Level Output Voltage Logic Low Level Output Voltage VOH VOL 0=LL DRV<1:0>=LH DRV<1:0>=HL DRV<1:0>=HH IOH< IOmax source, VDD=1.8 V IOL< IOmax sink, VDD=1.8 V Conditions 0.1 x VDD to 0.9 x VDD, CL= 10 pF, DRV<1:0>=HH 0.9 x VDD to 0.1 x VDD, CL= 10 pF, DRV<1:0>=HH Min -- -- -- VDD - 0.6 -- -100 5 0.1 0.9 1.5 1.8 VDD - 0.6 -- Typ -- -- -- -- -- -- -- 0.5 2.3 3.1 3.6 -- -- 0.6 100 25 0.8 3.5 4.8 5.4 -- 0.6 Max 8 8 1 Units ns ns pF V V nA A mA mA mA mA V V
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RFM42B/43B
Table 7. Absolute Maximum Ratings
Parameter VDD to GND Instantaneous VRF-peak to GND on TX Output Pin Sustained VRF-peak to GND on TX Output Pin Voltage on Digital Control Inputs Voltage on Analog Inputs Operating Temperature Range (special crystal is used on the module) T S Operating Temperature Range (Normal crystal is used on the module) TN Thermal Impedance JA Storage Temperature Range TSTG Value -0.3, +3.6 -0.3, +8.0 -0.3, +6.5 -0.3, VDD + 0.3 -0.3, VDD + 0.3 -40 to +85 -20 to +60 30 -55 to +125 Unit V V V V V C C C/W C
Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at or beyond these ratings in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Power Amplifier may be damaged if switched on without proper load or termination connected. TX matching network design will influence TX VRF-peak on TX output pin. Caution: ESD sensitive device.
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RFM42B/43B
2. Functional Description
HopeRF's RFM42B/43B are highly integrated,low cost,433/868/915MHz wireless ISM transmitters module . The wide operating voltage range of 1.8-3.6V and low current consumption makes the RFM42B/43B an ideal solution for battery powered applications. The RF carrier is generated by an integrated VCO and Fractional-N PLL synthesizer. The synthesizer is designed to support configurable data rates, output frequency, frequency deviation, and Gaussian filtering at 433MHz, 868MHz, 915MHz band. The transmit FSK data is modulated directly into the data stream and can be shaped by a Gaussian low-pass filter to reduce unwanted spectral content. The RFM42B's PA output power can be configured between and +20dBm in 3dB steps, while the RFM43B's +1 PA output power can be configured between -8 and +13 dBm in 3dB steps. The PA incorporates automatic ramp-up and ramp-down control to reduce unwanted spectral spreading. The RFM42B/43B is designed to work with a microcontroller to create a very low cost system. Voltage regulators are integrated on-chip which allows for a wide operating supply voltage range from +1.8 to +3.6V. A standard 4-pin SPI bus is used to communicate with an external microcontroller. Three configurable general purpose I/Os are available. A complete list of the available GPIO functions is available in " RFM42B/43B Register Descriptions."
2.1. Operating Modes
The RFM42B/43B provides several operating modes which can be used to optimize the power consumption for a given application. Table8 summarizes the operating modes of the RFM42B/43B. In general, any given operating mode may be classified as an active mode or a power saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception of the SHUTDOWN mode, all can be dynamically selected by sending the appropriate commands over the SPI. An "X" in any cell means that, in the given mode of operation, that block can be independently programmed to be either ON or OFF, without noticeably impacting the current consumption. The SPI circuit block includes the SPI interface hardware and the device register space. The 32 kHz OSC block includes the 32.768 kHz RC oscillator or 32.768 kHz crystal oscillator and wake-up timer. AUX (Auxiliary Blocks) includes the temperature sensor, general purpose ADC, and low-battery detector.
Table 8. Operating Modes
Mode Name Digital LDO SHUTDOWN OFF (Register contents lost) ON (Register contents retained) SPI OFF Circuit Blocks 32 kHz OSC AUX OFF OFF 30 MHz XTAL OFF PLL OFF PA OFF IVDD 15 nA
STANDBY SLEEP SENSOR READY TUNING TRANSMIT
ON ON ON ON ON ON
OFF ON X X X X
OFF X ON X X X
OFF OFF OFF ON ON ON
OFF OFF OFF OFF ON ON
OFF OFF OFF OFF OFF ON
450 nA 1 A 1 A 800 A 8.5 mA 30 mA*
*Note: Using RFM43B at +13dBm usin g recommended reference design.
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RFM42B/43B
3. Controller Interface
3.1. Serial Peripheral Interface (SPI)
The RFM42B/43B communicates with the host MCU over a standard 3-wire SPI interface: SCLK, SDI, and nSEL. The host MCU can read data from the device on the SDO output pin. A SPI transaction is a 16-bit sequence which consists of a Read-Write (R/W) select bit, followed by a 7-bit address field (ADDR), and an 8-bit data field (DATA) as demonstrated in Figure 1. The 7-bit address field is used to select one of the 128, 8-bit control registers. The R/W select bit determines whether the SPI transaction is a read or write transaction. If R/W = 1 it signifies a WRITE transaction, while R/W = 0 signifies a READ transaction. The contents (ADDR or DATA) are latched into the RFM42B/43B every eight clock cycles. The timing parameters for the SPI interface are shown in Table 9. The SCLK rate is flexible with a maximum rate of 10 MHz. Address
MSB
Data
LSB
SDI SCLK nSEL
RW A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx RW A7
Figure 1. SPI Timing Table 9. Serial Interface Timing Parameters
Symbol tCH tCL tDS tDH tDD tEN tDE tSS tSH tSW Parameter Clock high time Clock low time Data setup time Data hold time Output data delay time Output enable time Output disable time Select setup time Select hold time Select high period Min (nsec) 40 40 20 20 20 20 50 20 50 80
nSEL SDI SDO tEN tSW SCLK tSS tCL tCH tDS tDH tDD tSH tDE
Diagram
To read back data from the RFM42B /43B, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored n the SDI pin when R/W = 0. The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin. The READ function is shown in Figure 2. After the READ function is completed the SDO pin will remain at either a logic 1 or logic 0 state depending on the last data bit clocked out (D0). When nSEL goes high the SDO output pin will be pulled high by internal pullup.
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RFM42B/43B
First Bit
SDI SCLK
RW =0
Last Bit
D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X
A6 A5 A4 A3 A2 A1 A0
First Bit
SDO D7 D6 D5 D4 D3
Last Bit
D2 D1 D0
nSEL
Figure 2. SPI Timing--READ Mode
The SPI interface contains a burst read/write mode which allows for reading/writing sequential registers without having to re-send the SPI address. When the nSEL bit is held low while continuing to send SCLK pulses, the SPI interface will automatically increment the ADDR and read from/write to the next address. An example burst write transaction is illustrated in Figure 3 and a burst read in Figure 4. As long as nSEL is held low, input data will be latched into the RFM42B/43B every eight SCLK cycles.
First Bit
SDI SCLK nSEL
RW =1
Last Bit
D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X
A6 A5 A4 A3 A2 A1 A0
Figure 3. SPI Timing--Burst Write Mode
First Bit
SDI SCLK
RW =0
Last Bit A6 A5 A4 A3 A2 A1 A0
D7 =X D6 =X D5 =X D4 =X D3 =X D2 =X D1 =X D0 =X
First Bit
SDO D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
nSEL
Figure 4. SPI Timing--Burst Read Mode
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RFM42B/43B
3.2. Operating Mode Control
There are three primary states in the RFM42B/43B radio state machine: SHUTDOWN, IDLE, and TX (see Figure 5). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. "Register 07h. Operating Mode and Function Control 1" controls which operating mode/state is selected with the exception of SHUTDOWN which is controlled by SDN pin. The TX state may be reached automatically from any of the IDLE states by setting the txon bit in "Register 07h. Operating Mode and Function Control 1." Table 10 shows each of the operating modes with the time required to reach TX mode as well as the current consumption of each mode. The RFM42B/43B includes a low-power digital regulated supply (LPLDO) which is internally connected in parallel to the output of the main digital regulator (and is available externally at the VR_DIG pin). This common digital supply voltage is connected to all digital circuit blocks including the SPI and register space. The LPLDO has extremely low quiescent current consumption but limited current supply capability; it is used only in the IDLESTANDBY and IDLE-SLEEP modes. The main digital regulator is automatically enabled in all other modes.
SHUTDOWN SHUT DWN
IDLE*
TX *Five Different Options for IDLE
Figure 5. State Machine Diagram Table 10. Operating Modes Response Time
State/Mode Shut Down State Idle States: Standby Mode Sleep Mode Sensor Mode Ready Mode Tune Mode TX State Response Time to TX 16.8 ms 800 s 800 s 800 s 200 s 200 s NA Current in State/Mode [A] 15 nA 450 nA 1 A 1 A 800 A 8.5 mA RFM42B: 85 mA @ +20 dBm, RFM43B: 30 mA @ +13 dBm
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13
RFM42B/43B
3.2.1. SHUTDOWN State The SHUTDOWN state is the lowest current consumption state of the device with nominally less than 15 nA of current consumption. The SHUTDOWN state may be entered by driving the SDN pin high. The SDN pin should be held low in all states except the SHUTDOWN state. In the SHUTDOWN state, the contents of the registers are lost and there is no SPI access. When the chip is connected to the power supply, a POR will be initiated after the falling edge of SDN. 3.2.2. IDLE State There are five different modes in the IDLE state which may be selected by "Register 07h. Operating Mode and Function Control 1". All modes have a tradeoff between current consumption and response time to TX mode. This tradeoff is shown in Table 10. After the POR event, SWRESET, or exiting from the SHUTDOWN state the chip will default to the IDLE-READY mode. After a POR event the interrupt registers must be read to properly enter the SLEEP, SENSOR, or STANDBY mode and to control the 32 kHz clock correctly. 3.2.2.1. STANDBY Mode STANDBY mode has the lowest current consumption of the five IDLE states with only the LPLDO enabled to maintain the register values. In this mode the registers can be accessed in both read and write mode. The STANDBY mode can be entered by writing 0h to "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Additionally, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.2. SLEEP Mode In SLEEP mode the LPLDO is enabled along with the Wake-Up-Timer, which can be used to accurately wake-up the radio at specified intervals. See "7.6. Wake-Up Timer" for more information on the Wake - Up - Timer. SLEEP mode is entered by setting enwt = 1 (40h) in "Register 07h. Operating Mode and Function Control 1". If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. Also, the ADC should not be selected as an input to the GPIO in this mode as it will cause excess current consumption. 3.2.2.3. SENSOR Mode In SENSOR Mode either the Low Battery Detector, Temperature Sensor, or both may be enabled in addition to the LPLDO and Wake-Up-Timer. The Low Battery Detector can be enabled by setting enlbd = 1 in "Register 07h. Operating Mode and Function Control 1". See "7.4. Temperature Sensor " and "7.5. Low Battery Detector" for more information on these features. If an interrupt has occurred (i.e., the nIRQ pin = 0) the interrupt registers must be read to achieve the minimum current consumption. 3.2.2.4. READY Mode READY Mode is designed to give a fast transition time to TX mode with reasonable current consumption. In this mode the Crystal oscillator remains enabled reducing the time required to switch to TX mode by eliminating the crystal start-up time. READY mode is entered by setting xton = 1 in "Register 07h. Operating Mode and Function Control 1". To achieve the lowest current consumption state the crystal oscillator buffer should be disabled in "Register 62h. Crystal Oscillator Control and Test." 3.2.2.5. TUNE Mode In TUNE Mode the PLL remains enabled in addition to the other blocks enabled in the IDLE modes. This will give the fastest response to TX mode as the PLL will remain locked but it results in the highest current consumption. This mode of operation is designed for frequency hopping spread spectrum systems (FHSS). TUNE mode is entered by setting pllon = 1 in "Register 07h. Operating Mode and Function Control 1". It is not necessary to set xton to 1 for this mode, the internal state machine automatically enables the crystal oscillator.
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RFM42B/43B
3.2.3. TX State The TX state may be entered from any of the IDLE modes when the txon bit is set to 1 in "Register 07h. Operating Mode and Function Control 1". A built-in sequencer takes care of all the actions required to transition between states from enabling the crystal oscillator to ramping up the PA. The following sequence of events will occur automatically when going from STANDBY mode to TX mode by setting the txon bit. 1. Enable the main digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by an internal timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is "0", default value is "1"). 5. Wait until PLL settles to required transmit frequency (controlled by timer). 6. Activate power amplifier and wait until power ramping is completed (controlled by an internal timer). 7. Transmit packet. Steps in this sequence may be eliminated depending on which IDLE mode the chip is configured to prior to setting the txon bit. By default, the VCO and PLL are calibrated every time the PLL is enabled. 3.2.4. Device Status Add R/W Function/Description
02 R Device Status D7 ffovfl D6 ffunfl D5 Reserved D4 Reserved D3 freqerr D2 D1 cps[1] D0 cps[0] POR Def. --
The operational status of the chip can be read from "Register 02h. Device Status".
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RFM42B/43B
3.3. Interrupts
The RFM42B/43B is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h-04h) containing the active Interrupt Status bit. The nIRQ output signal will then be reset until the next change in status is detected. The interrupts must be enabled by the corresponding enable bit in the Interrupt Enable Registers (Registers 05h-06h). All enabled interrupt bits will be cleared when the microcontroller reads the interrupt status register. If the interrupt is not enabled when the event occurs it will not trigger the nIRQ pin, but the status may still be read at anytime in the Interrupt Status registers. Add R/W Function/Descript ion
03 04 R R Interrupt Status 1 Interrupt Status 2 Interrupt Enable 1 Interrupt Enable 2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def.
ifferr
itxffafull
itxffaem
Reserved iext
ipksent Reserved Reserved ilbd ichiprdy ipor
-- -- 00h 01h
Reserved Reserved Reserved Reserved iwut enfferr
05 R/W 06 R/W
entxffafull entxffaem Reserved enext enpksent Reserved Reserved enlbd enchiprdy enpor
Reserved Reserved Reserved Reserved enwut
See "RFM42B/43B Register Descriptions" for a complete list of interrupts.
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3.4. System Timing
The system timing for TX mode is shown in Figure 6. The figures demonstrate transitioning from STANDBY mode to TX mode through the built-in sequencer of required steps. The user only needs to program the desired mode, and the internal sequencer will properly transition the part from its current mode. The VCO will automatically calibrate at every frequency change or power up. The PLL T0 time is to allow for bias settling of the VCO. The PLL TS time is for the settling time of the PLL, which has a default setting of 100 s. The total time for PLL T0, PLL CAL, and PLL TS under all conditions is 200 s. Under certain applications, the PLL T0 time and the PLL CAL may be skipped for faster turn-around time. Contact applications support if faster turnaround time is desired.
PA RAMP DOWN
Configurable 5-20us, Recommend 5us
XTAL Settling Time
PRE PA RAMP PA RAMP UP
PLL CAL
PLL T0
PLLTS
TX Packet
600us
Configurable 0-310us, Recommend 100us
Configurable 5-20us, Recommend 5us
50us, May be skipped
Configurable 0-70us, Default = 50us
6us, Fixed
1.5Bits @DR
Figure 6. TX Timing
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RFM42B/43B
3.5. Frequency Control
For calculating the necessary frequency register settings it is recommended that customers use the HOPERF Register Calculator worksheet (in Microsoft Excel) available on the product website. These methods offe r a simple method to quickly determine the correct settings based on the application requirements. The following information can be used to calculated these values manually. 3.5.1. Frequency Programming In order to transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the RFM42B/43B . Note that this frequency is the center frequency of the desired channel. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3rd order) modulator. This modulator uses modulo 64000 accumulators. This design was made to obtain the desired frequency resolution of the synthesizer. The overall division ratio of the feedback loop consist of an integer part (N) and a fractional part (F).In a generic sense, the output frequency of the synthesizer is as follows:
f OUT 10 MHz ( N F )
The fractional part (F) is determined by three different values, Carrier Frequency (fc[15:0]), Frequency Offset (fo[8:0]), and Frequency Deviation (fd[7:0]). Due to the fine resolution and high loop bandwidth of the synthesizer, FSK modulation is applied inside the loop and is done by varying F according to the incoming data; this is discussed further in "3.5.4. Frequency Deviation" . Also, a fixed offset can be added to fine-tune the carrier frequency and counteract crystal tolerance errors. For simplicity assume that only the fc[15:0] register will determine the fractional component. The equation for selection of the carrier frequency is shown below:
f carrier 10 MHz (hbsel 1) ( N F )
fTX 10 MHz * ( hbsel 1) * ( fb[4 : 0] 24
Add R/W Function/Description
73 74 75 76 77 R/W R/W Frequency Offset 1 Frequency Offset 2 sbsel fc[15] fc[7] fc[14] fc[6] hbsel fc[13] fc[5] fb[4] fc[12] fc[4] fb[3] fc[11] fc[3] fb[2] fc[10] fc[2] D7 fo[7] D6 fo[6] D5 fo[5] D4 fo[4]
fc[15 : 0] ) 64000
D3 fo[3] D2 fo[2] D1 D0 POR Def. 00h 00h 35h BBh 80h fo[1] fo[0] fo[9] fo[8] fb[1] fb[0] fc[9] fc[8] fc[1] fc[0]
R/W Frequency Band Select R/W R/W Nominal Carrier Frequency 1 Nominal Carrier Frequency 0
The integer part (N) is determined by fb[4:0]. Additionally, the output frequency can be halved by connecting a /2 divider to the output. This divider is not inside the loop and is controlled by the hbsel bit in "Register 75h. Frequency Band Select". This effectively partitions the entire 240-960 MHz frequency range into two separate bands: High Band (HB) for hbsel = 1, and Low Band (LB) for hbsel = 0. The valid range of fb[4:0] is from 0 to 23. If a higher value is written into the register, it will default to a value of 23. The integer part has a fixed offset of 24 added to it as shown in the formula above. Table 11 demonstrates the selection of fb[4:0] for the corresponding frequency band. After selection of the fb (N) the fractional component may be solved with the following equation:
fTX fc[15 : 0] 10 MHz * (hbsel 1) fb[4 : 0] 24 * 64000
fb and fc are the actual numbers stored in the corresponding registers.
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Table 11. Frequency Band Selection
fb[4:0] Value N Frequency Band hbsel=0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 240-249.9 MHz 250-259.9 MHz 260-269.9 MHz 270-279.9 MHz 280-289.9 MHz 290-299.9 MHz 300-309.9 MHz 310-319.9 MHz 320-329.9 MHz 330-339.9 MHz 340-349.9 MHz 350-359.9 MHz 360-369.9 MHz 370-379.9 MHz 380-389.9 MHz 390-399.9 MHz 400-409.9 MHz 410-419.9 MHz 420-429.9 MHz 430-439.9 MHz 440-449.9 MHz 450-459.9 MHz 460-469.9 MHz 470-479.9 MHz hbsel=1 480-499.9 MHz 500-519.9 MHz 520-539.9 MHz 540-559.9 MHz 560-579.9 MHz 580-599.9 MHz 600-619.9 MHz 620-639.9 MHz 640-659.9 MHz 660-679.9 MHz 680-699.9 MHz 700-719.9 MHz 720-739.9 MHz 740-759.9 MHz 760-779.9 MHz 780-799.9 MHz 800-819.9 MHz 820-839.9 MHz 840-859.9 MHz 860-879.9 MHz 880-899.9 MHz 900-919.9 MHz 920-939.9 MHz 940-960 MHz
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RFM42B/43B
3.5.2. Easy Frequency Programming for FHSS While Registers 73h-77h may be used to program the carrier frequency of the RFM42B/43B, it is often easier to think in terms of "channels" or "channel numbers" rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h-77h, as described above. Registers 79h and 7Ah are then used to set a channel step size and channel number, relative to the nominal setting. The Frequency Hopping Step Size (fhs[7:0]) is set in increments of 10 kHz with a maximum channel step size of 2.56 MHz. The Frequency Hopping Channel Select Register then selects channels based on multiples of the step size.
Fcarrier Fnom fhs[7 : 0] ( fhch[7 : 0] 10kHz )
For example, if the nominal frequency is set to 900 MHz using Registers 73h-77h, the channel step size is set to 1 MHz using "Register 7Ah. Frequency Hopping Step Size," and "Register 79h. Frequency Hopping Channel Select" is set to 5d, the resulting carrier frequency would be 905 MHz. Once the nominal frequency and channel step size are programmed in the registers, it is only necessary to program the fhch[7:0] register in order to change the frequency. Add R/W
79 7A
Function/Description
D7
D6
D5
D4
D3
D2
D1
D0 fhch[0] fhs[0]
POR Def. 00h 00h
R/W Frequency Hopping Channel Select R/W Frequency Hopping Step Size
fhch[7] fhch[6] fhch[5] fhch[4] fhch[3] fhch[2] fhch[1] fhs[7] fhs[6] fhs[5] fhs[4] fhs[3] fhs[2] fhs[1]
3.5.3. Automatic State Transition for Frequency Change If registers 79h or 7Ah are changed in TX mode, the state machine will automatically transition the chip back to TUNE and change the frequency. This feature is useful to reduce the number of SPI commands required in a Frequency Hopping System. This in turn reduces microcontroller activity, reducing current consumption. The exception to this is during TX FIFO mode. If a frequency change is initiated during a TX packet, then the part will complete the current TX packet and will only change the frequency for subsequent packets. 3.5.4. Frequency Deviation The peak frequency deviation is configurable from 0.625 to 320 kHz. The Frequency Deviation (f) is controlled by the Frequency Deviation Register (fd), address 71 and 72h, and is independent of the carrier frequency setting. When enabled, regardless of the setting of the hbsel bit (high band or low band), the resolution of the frequency deviation will remain in increments of 625 Hz. When using frequency modulation the carrier frequency will deviate from the nominal center channel carrier frequency by f:
f fd [8 : 0] 625Hz f fd [8 : 0] f = peak deviation 625Hz
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RFM42B/43B
f
Frequency
fcarrier Time
Figure 7. Frequency Deviation
The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" for further details. Add R/W
71 72
Function/Description
D7
D6
D5
D4
D3
D2
D1
D0
POR Def. 00h 20h
R/W Modulation Mode Control 2 trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0] R/W Frequency Deviation fd[7] fd[6] fd[5] fd[4] fd[3] fd[2] fd[1] fd[0]
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RFM42B/43B
3.5.5. Frequency Offset Adjustment A frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment is implemented by shifting the Synthesizer Local Oscillator frequency. This register is a signed register so in order to get a negative offset it is necessary to take the twos complement of the positive offset number. The offset can be calculated by the following:
DesiredOffset 156.25 Hz (hbsel 1) fo[9 : 0]
fo[9 : 0]
DesiredOffset 156.25Hz (hbsel 1)
The adjustment range in high band is 160 kHz and in low band it is 80 kHz. For example to compute an offset of +50 kHz in high band mode fo[9:0] should be set to 0A0h. For an offset of -50 kHz in high band mode the fo[9:0] register should be set to 360h. Add R/W Function/Descript ion
73 74 R/W R/W Frequency Offset Frequency Offset D7 fo[7] D6 fo[6] D5 fo[5] D4 fo[4] D3 fo[3] D2 fo[2] D1 fo[1] fo[9] D0 fo[0] fo[8] POR Def. 00h 00h
3.5.6. TX Data Rate Generator The data rate is configurable between 0.123-256 kbps. For data rates below 30 kbps the "txdtrtscale" bit in register 70h should be set to 1. When higher data rates are used this bit should be set to 0. The TX date rate is determined by the following formula in kbps:
txdr 15:0 1 MHz DR_TX (kbps) = -------------------------------------------------16 + 5 txdtrtscale 2 DR_TX(kbps) 2 txdr[15:0] = --------------------------------------------------------------------------------------1 MHz
16 + 5 txdtrtscale
Add R/W Function/Description
6E 6F R/W R/W TX Data Rate 1 TX Data Rate 0
D7 txdr[15] txdr[7]
D6
D5
D4
D3
D2 txdr[10] txdr[2]
D1 txdr[9] txdr[1]
D0 txdr[8] txdr[0]
POR Def. 0Ah AAh
txdr[14] txdr[13] txdr[12] txdr[11] txdr[6] txdr[5] txdr[4] txdr[3]
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RFM42B/43B
4. Modulation Options
4.1. Modulation Type
The RFM42B/43B supports three different modulation options: Gaussian Frequency Shift Keying (GFSK), Frequency Shift Keying (FSK), and On-Off Keying (OOK). GFSK is the recommended modulation type as it provides the best performance and cleanest modulation spectrum. Figure 8 demonstrates the difference between FSK and GFSK for a Data Rate of 64 kbps. The time domain plots demonstrate the effects of the Gaussian filtering. The frequency domain plots demonstrate the spectral benefit of GFSK over FSK. The type of modulation is selected with the modtyp[1:0] bits in "Register 71h. Modulation Mode Control 2." Note that it is also possible to obtain an unmodulated carrier signal by setting modtyp[1:0] = 00. modtyp[1:0] 00 01 10 11 Modulation Source Unmodulated Carrier OOK FSK GFSK (enable TX Data CLK when direct mode is used)
TX Modulation Time Domain Waveforms -- FSK vs. GFSK
1.5 ModSpectrum_FSK ModSpectrum_GFSK SigData_FSK[0,::] 1.0 0.5 0.0 -0.5 -1.0 -1.5 1.0 SigData_GFSK[0,::] 0.5 0.0 -0.5 -1.0 0 50 100 150 200 250 300 350 400 450 500 time, usec
TX Modulation Spectrum -- FSK vs GFSK (Continuous PRBS)
-20 -40 -60 -80 -100 -20 -40 -60 -80 -100 -250
-200
-150
-100
-50
0 freq, KHz
50
100
150
200
250
DataRate 64000.0
TxDev 32000.0
BT_Filter 0.5
ModIndex 1.0
Figure 8. FSK vs. GFSK Spectrums
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RFM42B/43B
4.2. Modulation Data Source
The RFM42B/43B may be configured to obtain its modulation data from one of three different sources:FIFO mode, Direct Mode, and from a PN9 mode. In Direct Mode, the TX modulation data may be obtained from several different input pins. These options are set through the dtmod[1:0] field in "Register 71h. Modulation Mode Control 2." Add R/W Function/Description
71 R/W Modulation Mode Control 2 D7 D6 D5 D4 D3 D2 D1 D0 POR Def. 00h
trclk[1] trclk[0] dtmod[1] dtmod[0] eninv fd[8] modtyp[1] modtyp[0]
dtmod[1:0] 00 01 10 11 4.2.1. FIFO Mode
Data Source Direct Mode using TX Data via GPIO pin (GPIO configuration required) Direct Mode using TX Data via SDI pin (only when nSEL is high) FIFO Mode PN9 (internally generated)
In FIFO mode, the transmit data is stored in integrated FIFO register memory. The FIFOs are accessed via "Register 7Fh. FIFO Access," and are most efficiently accessed with burst read/write operation as discussed in "3.1. Serial Peripheral Interface (SPI)". In TX mode, the data bytes stored in FIFO memory are "packaged" together with other fields and bytes of information to construct the final transmit packet structure. These other potential fields include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler Registers (see Table12). If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into FIFO memory; no other fields (such as Preamble or Sync word are automatically added to the bytes stored in FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size, see "6. Data Handling and Packet Handler" . When in FIFO mode, the chip will automatically exit the TX State when either the ipksent or ipkvalid interrupt occurs. The chip will return to the IDLE mode state programmed in "Register 07h. Operating Mode and Function Control 1". For example, the chip may be placed into TX mode by setting the txon bit, but with the pllon bit additionally set. The chip will transmit all of the contents of the FIFO and the ipksent interrupt will occur. When this interrupt event occurs, the chip will clear the txon bit and return to TUNE mode, as indicated by the set state of the pllon bit. If no other bits are additionally set in register 07h (besides txon initially), then the chip will return to the STANDBY state.
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RFM42B/43B
4.2.2. Direct Mode For legacy systems that perform packet handling within an MCU or other baseband chip, it may not be desirable to use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In TX direct mode, the TX modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for transmission at a later time). A variety of pins may be configured for use as the TX Data input function. Furthermore, an additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin is required for FSK). Two options for the source of the TX Data are available in the dtmod[1:0] field, and various configurations for the source of the TX Data Clock may be selected through the trclk[1:0] field. trclk[1:0] 00 01 10 11 TX Data Clock Configuration No TX Clock (only for FSK) TX Data Clock is available via GPIO (GPIO needs programming accordingly as well) TX Data Clock is available via SDO pin (only when nSEL is high) TX Data Clock is available via the nIRQ pin
The eninv bit in SPI Register 71h will invert the TX Data; this is most likely useful for diagnostic and testing purposes. 4.2.2.1. Direct Synchronous Mode In TX direct mode, the chip may be configured for synchronous or asynchronous modes of modulation. In direct synchronous mode, the RFIC is configured to provide a TX Clock signal as an output to the external device that is providing the TX Data stream. This TX Clock signal is a square wave with a frequency equal to the programmed data rate. The external modulation source (e.g., MCU) must accept this TX Clock signal as an input and respond by providing one bit of TX Data back to the RFIC, synchronous with one edge of the TX Clock signal. In this fashion, the rate of the TX Data input stream from the external source is controlled by the programmed data rate of the RFIC; no TX Data bits are made available at the input of the RFIC until requested by another cycle of the TX Clock signal. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). All modulation types (FSK/GFSK/OOK) are valid in TX direct synchronous mode. As will be discussed in the next section, there are limits on modulation types in TX direct asynchronous mode. 4.2.2.2. Direct Asynchronous Mode In TX direct asynchronous mode, the RFIC no longer controls the data rate of the TX Data input stream. Instead, the data rate is controlled only by the external TX Data source; the RFIC simply accepts the data applied to its TX Data input pin, at whatever rate it is supplied. This means that there is no longer a need for a TX Clock output signal from the RFIC, as there is no synchronous "handshaking" between the RFIC and the external data source. The TX Data bits supplied by the external source are transmitted directly in real-time (i.e., not stored internally for later transmission). It is not necessary to program the data rate parameter when operating in TX direct asynchronous mode. The chip still internally samples the incoming TX Data stream to determine when edge transitions occur; however, rather than sampling the data at a pre-programmed data rate, the chip now internally samples the incoming TX Data stream at its maximum possible oversampling rate. This allows the chip to accurately determine the timing of the bit edge transitions without prior knowledge of the data rate. (Of course, it is still necessary to program the desired peak frequency deviation.) Only FSK and OOK modulation types are valid in TX Direct Asynchronous Mode; GFSK modulation is not available in asynchronous mode. This is because the RFIC does not have knowledge of the supplied data rate, and thus cannot determine the appropriate Gaussian lowpass filter function to apply to the incoming data. One advantage of this mode that it saves a microcontroller pin because no TX Clock output function is required. The primary disadvantage of this mode is the increase in occupied spectral bandwidth with FSK (as compared to GFSK).
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RFM42B/43B
4.2.2.3. Direct Mode using SPI or nIRQ Pins In certain applications it may be desirable to minimize the connections to the microcontroller or to preserve the GPIOs for other uses. For these cases it is possible to use the SPI pins and nIRQ as the modulation clock and data. The SDO pin can be configured to be the data clock by programming trclk = 10. If the nSEL pin is LOW then the function of the pin will be SPI data output. If the pin is high and trclk[1:0] is 10 then during TX mode the data clock will be available on the SDO pin. If trclk[1:0] is set to 11 and no interrupts are enabled in registers 05 or 06h, then the nIRQ pin can also be used as the TX data clock. The SDI pin can be configured to be the data source in TX mode if dtmod[1:0] = 01. In a similar fashion, if nSEL is LOW the pin will function as SPI data-in. If nSEL is HIGH then in TX mode it will be the data to be modulated and transmitted. Figure 9 demonstrates using SDI and SDO as the TX data and clock:
TX on command TX mode TX off command TX on command TX mode TX off command
nSEL
SDI SDO
SPI input
don't care
SPI input
MOD input
SPI input
don't care
SPI input
MOD output
SPI input
SPI output
don't care
SPI output
Data CLK Output
SPI output
don't care
SPI output
Data CLK Output
SPI output
Figure 9. Microcontroller Connections
If the SDO pin is not used for data clock then it may be programmed to be the interrupt function (nIRQ) by programming Reg 0Eh bit 3. 4.2.3. PN9 Mode In this mode the TX Data is generated internally using a pseudorandom (PN9 sequence) bit generator. The primary purpose of this mode is for use as a test mode to observe the modulated spectrum without having to provide data.
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RFM42B/43B
5. Internal Functional Blocks
This section provides an overview some of the key blocks of the internal radio architecture.
5.1. Synthesizer
An integrated Sigma Delta () Fractional-N PLL synthesizer capable of operating from 240-960 MHz is provided on-chip. Using a synthesizer has many advantages; it provides flexibility in choosing data rate, deviation, channel frequency, and channel spacing. The transmit modulation is applied directly to the loop in the digital domain through the fractional divider which results in very precise accuracy and control over the transmit deviation. Depending on the part, the PLL and - modulator scheme is designed to support any desired frequency and channel spacing in the range from 240-960 MHz with a frequency resolution of 156.25 Hz (Low band) or 312.5 Hz (High band). The transmit data rate can be programmed between 0.123-256 kbps, and the frequency deviation can be programmed between 1-320 kHz. These parameters may be adjusted via registers as shown in "3.5. Frequency Control".
Fref = 10 M
PFD
CP
LPF VCO
Selectable Divider
TX
N
TX Modulation
DeltaSigma
Figure 10. PLL Synthesizer Block Diagram
The reference frequency to the PLL is 10 MHz. The PLL utilizes a differential L-C VCO, with integrated on-chip inductors. The output of the VCO is followed by a configurable divider which will divide down the signal to the desired output frequency band. The modulus of this divider stage is controlled dynamically by the output from the - modulator. The tuning resolution is sufficient to tune to the commanded frequency with a maximum accuracy of 312.5 Hz anywhere in the range between 240-960 MHz. 5.1.1. VCO The output of the VCO is automatically divided down to the correct output frequency depending on the hbsel and fb[4:0] fields in "Register 75h. Frequency Band Select." The VCO integrates the resonator inductor, tuning varactor, so no external VCO components are required. The VCO uses a capacitance bank to cover the wide frequency range specified. The capacitance bank will automatically be calibrated every time the synthesizer is enabled. In certain fast hopping applications this might not be desirable so the VCO calibration may be skipped by setting the appropriate register.
5.2. Power Amplifier
The RFM42B contains an internal integrated power amplifier (PA) capable of transmitting at output levels between-1 and +20dBm. The RFM43B contains a PA which is capable of transmitting output levels between -8 to +13 dBm. The PA can chang the output power by adjusting txpow[2:0] will scale both the output power and current but the efficiency will not be constant. The PA output is ramped up and down to prevent unwanted spectral splatter.
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RFM42B/43B
5.2.1. Output Power Selection With the RFM42B,the output power is configurable in 3 dB steps with the txpow[2:0] field in "Register 6Dh. TX Power." Extra output power can allow the use of a cheaper, smaller antenna reducing the overall BOM cost. The higher power setting of the chip achieves maximum possible range, but of course comes at the cost of higher TX current consumption. However, depending on the duty cycle of the system, the effect on battery life may be insignificant. Contact HOPERF Support for help in evaluating this tradeoff. The +13 dBm output power of the RF43B is targeted at systems that require lower output power. The PA still offers high efficiency and a range of output power from -8 to +13 dBm. Add R/W Function/Description
6D R/W TX Power D7 D6 D5 D4 D3 D2 txpow[2] D1 txpow[1] D0 txpow[0] POR Def. 07h
txpow[2:0] 000 001 010 011 100 101 110 111
RFM42B Output Power +1 dBm +2 dBm +5 dBm +8 dBm +11 dBm +14 dBm +17 dBm +20 dBm
txpow[2:0] 000 001 010 011 100 101 110 111
RFM43B Output Power -8 dBm -5 dBm -2 dBm +1 dBm +4 dBm +7 dBm +10 dBm +13 dBm
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RFM42B/43B
5.3. Crystal Oscillator
The RFM42B/43B includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 s A parallel resonant 30MHz crystal is used on the module. Th e design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components. The crystal load capacitance can be digitally programmed to accommodate crystals with various load capacitance requirements and to adjust the frequency of the crystal oscillator. The tuning of the crystal load capacitance is programmed through the xlc[6:0] field of "Register 09h. 30 MHz Crystal Oscillator Load Capacitance." The total internal capacitance is 12.5 pF and is adjustable in approximately 127 steps (97fF/step). The xtalshift bit is a coarse shift in frequency but is not binary with xlc[6:0]. The crystal frequency adjustment can be used to compensate for crystal production tolerances. Utilizing the onchip temperature sensor and suitable control software, the temperature dependency of the crystal can be canceled. The typical value of the total on-chip capacitance Cint can be calculated as follows: Cint = 1.8 pF + 0.085 pF x xlc[6:0] + 3.7 pF x xtalshift Note that the coarse shift bit xtalshift is not binary with xlc[6:0]. The total load capacitance Cload seen by the crystal can be calculated by adding the sum of all external parasitic PCB capacitances Cext to Cint. If the maximum value of Cint (16.3pF) is not sufficient, an external capacitor can be added for exact tuning. The crystal oscillator frequency is divided down internally and may be output to the microcontroller through one of the GPIO pins for use as the System Clock. In this fashion, only one crystal oscillator is required for the entire system and the BOM cost is reduced. The available clock frequencies and GPIO configuration are discussed further in "7.2. Microcontroller Clock" .
Add R/W Function/Description
09 R/W Crystal Oscillator Load Capacitance
D7 xtalshift
D6 xlc[6]
D5 xlc[5]
D4 xlc[4]
D3 xlc[3]
D2 xlc[2]
D1 xlc[1]
D0 xlc[0]
POR Def. 40h
5.4. Regulators
There are a total of four regulators integrated onto the RFM42B/43B.With the exception of the digital regulator, all regulators are designed to operate with only internal decoupling. All regulators are designed to operate with an input supply voltage from +1.8 to +3.6V. A supply voltage should only be connected to the VDD pins.
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RFM42B/43B
6. Data Handling and Packet Handler
The internal modem is designed to operate with a packet including a 10101... preamble structure. To configure the modem to operate with packet formats without a preamble or other legacy packet structures contact customer support.
6.1. TX FIFO
A 64 byte FIFO is integrated into the chip for TX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst write, as described in "3.1. Serial Peripheral Interface (SPI) " , to address 7Fh will write data to the TX FIFO.
TX FIFO
TX FIFO Almost Full Threshold
TX FIFO Almost Empty Threshold
Figure 11. FIFO Threshold
The TX FIFO has two programmable thresholds. An interrupt event occurs when the data in the TX FIFO reaches these thresholds. The first threshold is the FIFO almost full threshold, txafthr[5:0]. The value in this register corresponds to the desired threshold value in number of bytes. When the data being filled into the TX FIFO crosses this threshold limit, an interrupt to the microcontroller is generated so the chip can enter TX mode to transmit the contents of the TX FIFO. The second threshold for TX is the FIFO almost empty Threshold, txaethr[5:0]. When the data being shifted out of the TX FIFO drops below the almost empty threshold an interrupt will be generated. The microcontroller will need to switch out of TX mode or fill more data into the TX FIFO. The transceiver can be configured so that when the TX FIFO is empty it will automatically exit the TX state and return to one of the low power states. When TX is initiated, it will transmit the number of bytes programmed into the packet length field (Reg 3Eh). When the packet ends, the chip will return to the state specified in register 07h. For example, if 08h is written to address 07h then the chip will return to the STANDBY state. If 09h is written then the chip will return to the READY state.
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RFM42B/43B
Add R/W Function/D escription
08 R/W D7 D6 D5 D4 D3 autotx D2 D1 D0 ffclrtx POR Def. 00h
Operating & Reserved Reserved Reserved Reserved Function Control 2 TX FIFO Control 1 TX FIFO Control 2 Reserved Reserved txafthr[5] txafthr[4]
Reserved Reserved
7C 7D
R/W R/W
txafthr[3] txafthr[2] txafthr[1] txafthr[0]
37h 04h
Reserved Reserved txaethr[5] txaethr[4] txaethr[3] txaethr[2] txaethr[1] txaethr[0]
The TX FIFO may be cleared or reset with the ffclrtx bit in "Register 08h. Operating Mode and Function Control 2." All interrupts may be enabled by setting the Interrupt Enabled bits in "Register 05h. Interrupt Enable 1" and "Register 06h. Interrup t Enable 2,". If the interrupts are not enabled the function will not generate an interrupt on the nIRQ pin but the bits will still be read correctly in the Interrupt Status registers.
6.2. Packet Configuration
When using the FIFO, automatic packet handling may be enabled for the TX mode. "Register 30h. Data Access Control" through "Register 3Eh. Packet Length," control the configuration for Packet Handling. The usual fields for network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be configured to be automatically added to the data payload. The fields needed for packet generation normally change infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload greatly reduces the amount of communication between the microcontroller and the RF 42B/43B and reduces the required computational power of the microcontroller. The general packet structure is shown in Figure 12. The length of each field is shown below the field. The preamble pattern is always a series of alternating ones and zeroes, starting with a zero. All the fields have programmable lengths to accommodate different applications. The most common CRC polynominals are available for selection.
Packet Length Sync Word TX Header
Preamble
Data
CRC
1-512 Bytes
1-4 Bytes 0-4 Bytes 0 or 1 Byte 0 or 2 Bytes
Figure 12. Packet Structure
An overview of the packet handler configuration registers is shown in Table 12.
6.3. Packet Handler TX Mode
If the TX packet length is set the packet handler will send the number of bytes in the packet length field before returning to IDLE mode and asserting the packet sent interrupt. To resume sending data from the FIFO the microcontroller needs to command the chip to re-enter TX mode. Figure 14 provides an example transaction where the packet length is set to three bytes.
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RFM42B/43B
D ata D ata D ata D ata D ata D ata D ata D ata D ata 1 2 3 4 5 6 7 8 9
} } }
This w ill be sent in the first transm ission
This w ill be sent in the second transm ission This w ill be sent in the third transm ission
Figure 13. Multiple Packets in TX Packet Handler Table 12. Packet Handler Registers
Add
30 31 32 33 34 36 37 38 39 3A 3B 3C 3D 3E R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Header Control 2 Preamble Length Sync Word 3 Sync Word 2 Sync Word 1 Sync Word 0 Transmit Header 3 Transmit Header 2 Transmit Header 1 Transmit Header 0 Transmit Packet Length skipsyn prealen[7] sync[31] sync[23] sync[15] sync[7] txhd[31] txhd[23] txhd[15] txhd[7] pklen[7] hdlen[2] prealen[6] sync[30] sync[22] sync[14] sync[6] txhd[30] txhd[22] txhd[14] txhd[6] pklen[6]
R/W
R/W R
Function/Description
Data Access Control EzMAC status
D7
Reserved 0
D6
lsbfrst Reserved
D5
crcdonly Reserved hdlen[1] prealen[5] sync[29] sync[21] sync[13] sync[5] txhd[29] txhd[21] txhd[13] txhd[5] pklen[5]
D4
skip2ph Reserved hdlen[0] prealen[4] sync[28] sync[20] sync[12] sync[4] txhd[28] txhd[20] txhd[12] txhd[4] pklen[4]
D3
enpactx Reserved fixpklen prealen[3] sync[27] sync[19] sync[11] sync[3] txhd[27] txhd[19] txhd[11] txhd[3] pklen[3]
D2
encrc Reserved synclen[1] prealen[2] sync[26] sync[18] sync[10] sync[2] txhd[26] txhd[18] txhd[10] txhd[2] pklen[2]
D1
crc[1] pktx synclen[0] prealen[1] sync[25] sync[17] sync[9] sync[1] txhd[25] txhd[17] txhd[9] txhd[1] pklen[1]
D0
crc[0] pksent prealen[8] prealen[0] sync[24] sync[16] sync[8] sync[0] txhd[24] txhd[16] txhd[8] txhd[0] pklen[0]
POR Def.
8Dh -- 22h 08h 2Dh D4h 00h 00h 00h 00h 00h 00h 00h
Reserved
32
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RFM42B/43B
6.4. Data Whitening, Manchester Encoding, and CRC
Data whitening can be used to avoid extended sequences of 0s or 1s in the transmitted data stream to achieve a more uniform spectrum. When enabled, the payload data bits are XORed with a pseudorandom sequence output from the built-in PN9 generator. The generator is initialized at the beginning of the payload. The receiver recovers the original data by repeating this operation. Manchester encoding can be used to ensure a dc-free transmission and good synchronization properties. When Manchester encoding is used, the effective datarate is unchanged but the actual datarate (preamble length, etc.) is doubled due to the nature of the encoding. The effective datarate when using Manchester encoding is limited to 128 kbps. The implementation of Manchester encoding is shown in Figure 15. Data whitening and Manchester encoding can be selected with "Register 70h. Modulation Mode Control 1". The CRC is configured via "Register 30h. Data Access Control". Figure 14 demonstrates the portions of the packet which have Manchester encoding, data whitening, and CRC applied. CRC can be applied to only the data portion of the packet or to the data, packet length and header fields. Figure 15 provides an example of how the Manchester encoding is done and also the use of the Manchester invert (enmaniv) function.
Manchester Whitening CRC
CRC (Over data only)
Preamble
Sync
Header/ Address
PK Length
Data
CRC
Figure 14. Operation of Data Whitening, Manchester Encoding, and CRC
Data before Manchester 1 1 1 1 1 Preamble = 0xFF 1 1 1 0 0 0 1 0 First 4bits of the synch. word = 0x2 Data after Machester ( manppol = 1, enmaninv = 0) Data after Machester ( manppol = 1, enmaninv = 1)
Data before Manchester 0 0 0 0 0 Preamble = 0x00 0 0 0 0 0 0 1 0 First 4bits of the synch. word = 0x2 Data after Machester ( manppol = 0, enmaninv = 0) Data after Machester ( manppol = 0, enmaninv = 1)
Figure 15. Manchester Coding Example
6.5. Synchronization Word Configuration
The synchronization word length can be configured in Reg 33h, synclen[1:0]. The expected or transmitted sync word can be configured from 1 to 4 bytes as defined below: synclen[1:0] = 00--Transmitted Synchronization Word (sync word) 3. synclen[1:0] = 01--Transmitted Synchronization Word 3 first, followed by sync word 2. synclen[1:0] = 10--Transmitted Synchronization Word 3 first, followed by sync word 2, followed by sync word 1. synclen[1:0] = 1--Transmitted Synchronization Word 3 first, followed by sync word 2, followed by sync word 1, followed by sync word 0. The sync is transmitted in the following sequence: sync 3sync 2sync 1sync 0. The sync word values can be programmed in Registers 36h-39h.
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RFM42B/43B
6.6. TX Retransmission and Auto TX
The RFM42B/43B is capable of automatically retransmitting the last packet loaded in the TX FIFO. Automatic retransmission is set by entering the TX state with the txon bit without reloading the TX FIFO. This feature is useful for beacon transmission or when retransmission is required due to the absence of a valid acknowledgement. Only packets that fit completely in the TX FIFO can be automatically retransmitted. An automatic transmission function is available, allowing the radio to automatically start or stop a transmission depending on the amount of data in the TX FIFO. When autotx is set in "Register 08. Operating & Function Control 2," the transceiver will automatically enter the TX state when the TX FIFO almost full threshold is exceeded. Packets will be transmitted according to the configured packet length. To stop transmitting, clear the packet sent or TX FIFO almost empty interrupts must be cleared by reading register.
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RFM42B/43B
7. Auxiliary Functions
7.1. Smart Reset
The RFM42B/43B contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce a reliable reset signal under any circumstances. Reset will be initiated if any of the following conditions occur:

Initial power on, VDD starts from gnd: reset is active till VDD reaches VRR (see table); When VDD decreases below VLD for any reason: reset is active till VDD reaches VRR;
A software reset via "Register 08h. Operating Mode and Function Control 2,": reset is active for time TSWRST VDD glitch when the supply voltage exceeds the following time functioned limit:
VDD nom. VDD(t)
reset limit: 0.4V+t*0.2V/ms
0.4V
actual VDD(t) showing glitch
Reset TP
t=0, VDD starts to rise reset: Vglitch>=0.4+t*0.2V/ms
t
Figure 16. POR Glitch Parameters Table 13. POR Parameters
Parameter Release Reset Voltage Power-On VDD Slope Low VDD Limit Software Reset Pulse Threshold Voltage Reference Slope VDD Glitch Reset Pulse Symbol VRR SVDD VLD TSWRST VTSD k TP Also occurs after SDN, and initial power on tested VDD slope region VLDThe reset will initialize all registers to their default values. The reset signal is also available for output and use by the microcontroller by using the default setting for GPIO_0. The inverted reset signal is available by default on GPIO_1.
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RFM42B/43B
7.2. Microcontroller Clock
The 30 MHz crystal oscillator frequency is divided down internally and may be output to the microcontroller through GPIO2. This feature is useful to lower BOM cost by using only one crystal in the system. The system clock frequency is selectable from one of 8 options, as shown below. Except for the 32.768 kHz option, all other frequencies are derived by dividing the crystal oscillator frequency. The 32.768 kHz clock signal is derived from an internal RC oscillator or an external 32 kHz crystal. The default setting for GPIO2 is to output the microcontroller clock signal with a frequency of 1 MHz. Add R/W
0A R/W
Function/Description
Microcontroller Output Clock
D7
D6
D5 clkt[1]
D4 clkt[0]
D3 enlfc
D2
D1
D0
POR Def. 0Bh
mclk[2] mclk[1] mclk[0]
mclk[2:0] 000 001 010 011 100 101 110 111
Clock Frequency 30 MHz 15 MHz 10 MHz 4 MHz 3 MHz 2 MHz 1 MHz 32.768 kHz
If the microcontroller clock option is being used there may be the need of a system clock for the microcontroller while the RFM42B/43B is in SLEEP mode. Since the crystal oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called enable low frequency clock and is enabled by the enlfc bit in "Register 0Ah. Microcontroller Output Clock." When enlfc = 1 and the chip is in SLEEP mode then the 32.768 kHz clock will be provided to the microcontroller as the system clock, regardless of the setting of mclk[2:0]. For example, if mclk[2:0] = 000, 30 MHz will be provided through the GPIO output pin to the microcontroller as the system clock in all IDLE or TX states. When the chip enters SLEEP mode, the system clock will automatically switch to 32.768 kHz from the RC oscillator or 32.768 XTAL. Another available feature for the microcontroller clock is the clock tail, clkt[1:0] in "Register 0Ah. Microcontroller Output Clock." If the low frequency clock feature is not enabled (enlfc = 0), then the system clock to the microcontroller is disabled in SLEEP mode. However, it may be useful to provide a few extra cycles for the microcontroller to complete its operation prior to the shutdown of the system clock signal. Setting the clkt[1:0] field will provide additional cycles of the system clock before it shuts off. clkt[1:0] 00 01 10 11 Clock Tail 0 cycles 128 cycles 256 cycles 512 cycles
If an interrupt is triggered, the microcontroller clock will remain enabled regardless of the selected mode. As soon as the interrupt is read the state machine will then move to the selected mode. The minimum current consumption will not be achieved until the interrupt is read. For instance, if the chip is commanded to SLEEP mode but an interrupt has occurred the 30 MHz XTAL will not be disabled until the interrupt has been cleared.
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RFM42B/43B
7.3. General Purpose ADC
An 8-bit SAR ADC is integrated for general purpose use, as well as for digitizing the on-chip temperature sensor reading. Registers 0Fh "ADC Configuration", 10h "Sensor Offset" and 4Fh "Amplifier Offset" can be used to configure the ADC operation. Every time an ADC conversion is desired, bit 7 "adcstart/adcbusy" in "Register 1Fh. Clock Recovery Gearshift Override" must be set to 1. This is a self clearing bit that will be reset to 0 at the end of the conversion cycle of the ADC. The conversion time for the ADC is 350 s. After this time or when the "adcstart/adcbusy" bit is cleared, then the ADC value may be read out of "Register 11h. ADC Value." The architecture of the ADC is shown in Figure 17. The signal and reference inputs of the ADC are selected by adcsel[2:0] and adcref[1:0] in register 0Fh "ADC Configuration", respectively. The default setting is to read out the temperature sensor using the bandgap voltage (VBG) as reference. With the VBG reference the input range of the ADC is from 0-1.02 V with an LSB resolution of 4 mV (1.02/255). Changing the ADC reference will change the LSB resolution accordingly. A differential multiplexer and amplifier are provided for interfacing external bridge sensors. The gain of the amplifier is selectable by adcgain[1:0] in Register 0Fh. The majority of sensor bridges have supply voltage (VDD) dependent gain and offset. The reference voltage of the ADC can be changed to either VDD/2 or VDD/3. A programmable VDD dependent offset voltage can be added using soffs[3:0] in register 10h.
Diff. MUX Diff. Amp.
GPIO0 GPIO1 GPIO2
adcsel [2:0]
Temperature Sensor
... ...
Input MUX aoffs [4:0] soffs [3:0] adcgain [1:0] adcsel [2:0] Ref MUX VDD / 3 VDD / 2 VBG (1.2V) adcref [1:0]
Figure 17. General Purpose ADC Architecture
Add
0F 10 11
...
8-bit ADC
Vin Vref
0 -1020mV / 0-255
adc [7:0]
...
R/W
R/W R/W R
Function/Description
ADC Configuration Sensor Offset ADC Value
D7
adcstart/adcbusy
D6
D5
D4
adcsel[0]
D3
adcref[1] soffs[3]
D2
adcref[0] soffs[2] adc[2]
D1
D0
POR Def.
00h 00h --
adcsel[2] adcsel[1]
adcgain[1] adcgain[0] soffs[1] adc[1] soffs[0] adc[0]
adc[7]
adc[6]
adc[5]
adc[4]
adc[3]
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RFM42B/43B
7.4. Temperature Sensor
An integrated on-chip analog temperature sensor is available. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on the analog test bus. The temperature sensor value may be digitized using the general-purpose ADC and read out over the SPI through "Register 10h. ADC Sensor Amplifier Offset." The range of the temperature sensor is configurable. Table 14 lists the settings for the different temperature ranges and performance. To use the Temp Sensor: 1. Set the input for ADC to the temperature sensor, "Register 0Fh. ADC Configuration"--adcsel[2:0] = 000 2. Set the reference for ADC, "Register 0Fh. ADC Configuration"--adcref[1:0] = 00 3. Set the temperature range for ADC, "Register 12h. Temperature Sensor Calibration"--tsrange[1:0] 4. Set entsoffs = 1, "Register 12h. Temperature Sensor Calibration" 5. Trigger ADC reading, "Register 0Fh. ADC Configuration"--adcstart = 1 6. Read temperature value--Read contents of "Register 11h. ADC Value" Add R/W Function/Description
12 13 R/W Temperature Sensor Control D7
tsrange[1]
D6
tsrange[0]
D5
entsoffs
D4
entstrim
D3
tstrim[3]
D2
tstrim[2]
D1
D0
POR Def. 20h 00h
vbgtrim[1] vbgtrim[0]
R/W Temperature Value Offset
tvoffs[7]
tvoffs[6]
tvoffs[5]
tvoffs[4]
tvoffs[3]
tvoffs[2]
tvoffs[1]
tvoffs[0]
Table 14. Temperature Sensor Range
entoff 1 1 1 1 0* tsrange[1] 0 0 1 1 1 tsrange[0] 0 1 0 1 0 Temp. range -64 ... 64 -64 ... 192 0 ... 128 -40 ... 216 0 ... 341 Unit C C C F K Slope 8 mV/C 4 mV/C 8 mV/C 4 mV/F 3 mV/K ADC8 LSB 0.5 C 1 C 0.5 C 1 F 1.333 K
*Note: Absolute temperature mode, no temperature shift. This mode is only for test purposes. POR value of EN_TOFF is 1.
The slope of the temperature sensor is very linear and monotonic. For absolute accuracy better than 10 C calibration is necessary. The temperature sensor may be calibrated by setting entsoffs = 1 in "Register 12h. Temperature Sensor Control" and setting the offset with the tvoffs[7:0] bits in "Register 13h. Temperature Value Offset." This method adds a positive offset digitally to the ADC value that is read in "Register 11h. ADC Value." The other method of calibration is to use the tstrim which compensates the analog circuit. This is done by setting entstrim = 1 and using the tstrim[2:0] bits to offset the temperature in "Register 12h. Temperature Sensor Control." With this method of calibration, a negative offset may be achieved. With both methods of calibration better than 3 C absolute accuracy may be achieved. The different ranges for the temperature sensor and ADC8 are demonstrated in Figure 18. The value of the ADC8 may be translated to a temperature reading by ADC8Value x ADC8 LSB + Lowest Temperature in Temp Range. For instance for a tsrange = 00, Temp = ADC8Value x 0.5 - 64.
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RFM42B/43B
Temperature Measurement with ADC8
300
250 200 ADC Value Sensor Range 0 150 100 Sensor Range 1 Sensor Range 2 Sensor Range 3
50 0 -40 -20 0 20 40 60 80 100 Temperature [Celsius]
Figure 18. Temperature Ranges using ADC8
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RFM42B/43B
7.5. Low Battery Detector
A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold." When the digitized battery voltage reaches this threshold an interrupt will be generated on the nIRQ pin to the microcontroller. The microcontroller can confirm source of the interrupt by reading "Register 03h. Interrupt/Status 1" and "Register 04h. Interrupt/Status 2," If the LBD is enabled while the chip is in SLEEP mode, it will automatically enable the RC oscillator which will periodically turn on the LBD circuit to measure the battery voltage. The battery voltage may also be read out through "Register 1Bh. Battery Voltage Level" at any time when the LBD is enabled. The low battery detect function is enabled by setting enlbd=1 in "Register 07h. Operating Mode and Function Control 1". Ad
1A 1B
R/W
R/W R
Function/Description
Low Battery Detector Threshold Battery Voltage Level
D7
D6
D5
D4 lbdt[4]
D3 lbdt[3]
D2 lbdt[2]
D1 lbdt[1]
D0 lbdt[0]
POR Def. 14h --
0
0
0
vbat[4] vbat[3] vbat[2] vbat[1] vbat[0]
The LBD output is digitized by a 5-bit ADC. When the LBD function is enabled, enlbd = 1 in "Register 07h. Operating Mode and Function Control 1", the battery voltage may be read at anytime by reading "Register 1Bh. Battery Voltage Level." A battery voltage threshold may be programmed in "Register 1Ah. Low Battery Detector Threshold." When the battery voltage level drops below the battery voltage threshold an interrupt will be generated on the nIRQ pin to the microcontroller if the LBD interrupt is enabled in "Register 06h. Interrupt Enable 2," The microcontroller will then need to verify the interrupt by reading the interrupt status register, addresses 03 and 04h. The LSB step size for the LBD ADC is 50 mV, with the ADC range demonstrated in the table below. If the LBD is enabled the LBD and ADC will automatically be enabled every 1 s for approximately 250 s to measure the voltage which minimizes the current consumption in Sensor mode. Before an interrupt is activated four consecutive readings are required.
BatteryVoltage 1.7 50mV ADCValue
ADC Value 0 1 2 ... 29 30 31 VDD Voltage [V] < 1.7 1.7-1.75 1.75-1.8 ... 3.1-3.15 3.15-3.2 > 3.2
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RFM42B/43B
7.6. Wake-Up Timer
The chip contains an integrated wake-up timer which can be used to periodically wake the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP mode. If enwt = 1 in "Register 07h. Operating Mode and Function Control 1" when entering SLEEP mode, the wake-up timer will count for a time specified defined in Registers 14-16h, "Wake Up Timer Period." At the expiration of this period an interrupt will be generated on the nIRQ pin if this interrupt is enabled. The microcontroller will then need to verify the interrupt by reading the Registers 03h-04h, "Interrupt Status 1 & 2". The wake-up timer value may be read at any time by the wtv[15:0] read only registers 13h-14h. The formula for calculating the Wake-Up Period is the following:
WUT
WUT Register wtr[3:0] wtd[1:0] wtm[15:0]
4 M 2R ms 32 . 768
Description R Value in Formula D Value in Formula M Value in Formula
Use of the D variable in the formula is only necessary if finer resolution is required than can be achieved by using the R value. Add R/W Function/Description
14 15 16 17 18 R/W R/W R/W R R Wake-Up Timer Period 1 Wake-Up Timer Period 2 Wake-Up Timer Period 3 Wake-Up Timer Value 1 Wake-Up Timer Value 2 D7 D6 D5 wtr[3] D4 wtr[2] D3 wtr[1] D2 wtr[0] D1 wtd[1] D0 wtd[0] POR Def. 00h 00h 00h -- --
wtm[15] wtm[14] wtm[13] wtm[12] wtm[11] wtm[10] wtm[9] wtm[8] wtm[7] wtv[15] wtv[7] wtm[6] wtv[14] wtv[6] wtm[5] wtv[13] wtv[5] wtm[4] wtv[12] wtv[4] wtm[3] wtv[11] wtv[3] wtm[2] wtv[10] wtv[2] wtm[1] wtm[0] wtv[9] wtv[1] wtv[8] wtv[0]
There are two different methods for utilizing the wake-up timer (WUT) depending on if the WUT interrupt is enabled in "Register 06h. Interrupt Enable 2,". If the WUT interrupt is enabled then nIRQ pin will go low when the timer expires. The chip will also change state so that the 30 MHz XTAL is enabled so that the microcontroller clock output is available for the microcontroller to use to process the interrupt. The other method of use is to not enable the WUT interrupt and use the WUT GPIO setting. In this mode of operation the chip will not change state until commanded by the microcontroller. The different modes of operating the WUT and the current consumption impacts are demonstrated in Figure 19. A 32 kHz XTAL may also be used for better timing accuracy. By setting the x32 ksel bit in "Register 07h. Operating & Function Control 1," GPIO0 is automatically reconfigured so that an external 32 kHz XTAL may be connected to this pin. In this mode, the GPIO0 is extremely sensitive to parasitic capacitance, so only the XTAL should be connected to this pin with the XTAL physically located as close to the pin as possible. Once the x32 ksel bit is set, all internal functions such as WUT, microcontroller clock, and LDC mode will use the 32 kHz XTAL and not the 32 kHz RC oscillator.
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RFM42B/43B
Interrupt Enable enwut =1 ( Reg 06h)
WUT Period GPIOX =00001
nIRQ
SPI Interrupt Read
Chip State Sleep Ready 1.5 mA Sleep Ready 1.5 mA 1 uA Sleep Ready 1.5 mA 1 uA Sleep
Current Consumption
1 uA
Interrupt Enable enwut =0 ( Reg 06h)
WUT Period GPIOX =00001
nIRQ
SPI Interrupt Read
Chip State Sleep
Current Consumption 1 uA
Figure 19. WUT Interrupt and WUT Operation
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RFM42B/43B
7.7. GPIO Configuration
Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, TRSW control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode all the GPIO pads are pulled low.
Note: The ADC should not be selected as an input to the GPIO in Standby or Sleep Modes and will cause excess current consumption.
Add R/W
0B 0C 0D 0E R/W R/W R/W R/W
Function/ Description
GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration
D7
D6
D5
D4
D3
D2
D1
D0
POR Def.
gpio0drv[1] gpio0drv[0] gpio1drv[1] gpio1drv[0] gpio2drv[1] gpio2drv[0] extitst[2]
pup0 pup1 pup2
gpio0[4] gpio0[3] gpio0[2] gpio0[1] gpio0[0] gpio1[4] gpio1[3] gpio1[2] gpio1[1] gpio1[0] gpio2[4] gpio2[3] gpio2[2] gpio2[1] gpio2[0] itsdo dio2 dio1 dio0
00h 00h 00h 00h
extitst[1] extitst[0]
The GPIO settings for GPIO1 and GPIO2 are the same as for GPIO0 with the exception of the 00000 default setting. The default settings for each GPIO are listed below: GPIO GPIO0 GPIO1 GPIO2 00000--Default Setting POR POR Inverted Microcontroller Clock
For a complete list of the available GPIO's see " RFM42B/43B Register Descriptions." The GPIO drive strength may be adjusted with the gpioXdrv[1:0] bits. Setting a higher value will increase the drive strength and current capability of the GPIO by changing the driver size. Special care should be taken in setting the drive strength and loading on GPIO2 when the microcontroller clock is used. Excess loading or inadequate drive may contribute to increased spurious emissions.
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RFM42B/43B
8. Reference Design
Figure 20A.RFM42B Reference Design Schematic
Figure 20B.RFM43B Reference Design Schematic
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Freq. band RDC LC C0 L0 CM LM CM2 LM2 CM3 [MHz] [Ohm] [nH] [pF] [nH] [pF] [nH] [pF] [nH] [pF]
RFM42B/43B
9. Register Table and Descriptions
Table 15. Register Descriptions
Add 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C-2F 30 31 32 33 34 36 37 38 39 3A 3B 3C 3D 3E 4F 60 62 6D 6E 6F 70 71 72 73 74 75 76 77 79 7A 7C 7D 7E 7F R/W R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R R Function/Desc Device Version Device Status Interrupt Status 1 Interrupt Status 2 Interrupt Enable 1 Interrupt Enable 2 Operating & Function Control 1 Operating & Function Control 2 Crystal Oscillator Load Capacitance Microcontroller Output Clock GPIO0 Configuration GPIO1 Configuration GPIO2 Configuration I/O Port Configuration ADC Configuration ADC Sensor Amplifier Offset ADC Value Temperature Sensor Control Temperature Value Offset Wake-Up Timer Period 1 Wake-Up Timer Period 2 Wake-Up Timer Period 3 Wake-Up Timer Value 1 Wake-Up Timer Value 2 D7 0 ffovfl ifferr Reserved enfferr Reserved swres Reserved xtalshft Reserved gpio0drv[1] gpio1drv[1] gpio2drv[1] Reserved adcstart/adcdone Reserved adc[7] tsrange[1] tvoffs[7] Reserved wtm[15] wtm[7] wtv[15] wtv[7] Reserved 0 Reserved 0 Reserved prealen[7] sync[31] sync[23] sync[15] sync[7] txhd[31] txhd[23] txhd[15] txhd[7] pklen[7] Reserved pwst[2] papeakval txdr[15] txdr[7] Reserved trclk[1] fd[7] fo[7] Reserved Reserved fc[15] fc[7] fhch[7] fhs[7] Reserved Reserved fifod[7] D6 0 ffunfl itxffafull Reserved entxffafull Reserved enlbd Reserved xlc[6] Reserved gpio0drv[0] gpio1drv[0] gpio2drv[0] extitst[2] adcsel[2] Reserved adc[6] tsrange[0] tvoffs[6] Reserved wtm[14] wtm[6] wtv[14] wtv[6] Reserved 0 lsbfrst Reserved hdlen[2] prealen[6] sync[30] sync[22] sync[14] sync[6] txhd[30] txhd[22] txhd[14] txhd[6] pklen[6] Reserved pwst[1] papeaken txdr[14] txdr[6] Reserved trclk[0] fd[6] fo[6] Reserved sbsel fc[14] fc[6] fhch[6] fhs[6] Reserved Reserved fifod[6] D5 0 itxffaem Reserved entxffaem Reserved enwt Reserved xlc[5] clkt[1] pup0 pup1 pup2 extitst[1] adcsel[1] Data D4 vc[4] Reserved Reserved Reserved Reserved Reserved x32ksel Reserved xlc[4] clkt[0] gpio0[4] gpio1[4] gpio2[4] extitst[0] adcsel[0] D3 vc[3] reserved iext iwut enext enwut txon autotx xlc[3] enlfc gpio0[3] gpio1[3] gpio2[3] itsdo adcref[1] adcoffs[3] adc[3] tstrim[3] tvoffs[3] wtr[3] wtm[11] wtm[3] wtv[11] wtv[3] lbdt[3] vbat[3] enpactx Reserved fixpklen prealen[3] sync[27] sync[19] sync[11] sync[3] txhd[27] txhd[19] txhd[11] txhd[3] pklen[3] adc8[3] enbias2x Ina_sw txdr[11] txdr[3] manppol eninv fd[3] fo[3] Reserved fb[3] fc[11] fc[3] fhch[3] fhs[3] txafthr[3] txaethr[3] fifod[3] D2 vc[2] reserved ipksent ilbd enpksent enlbd Reserved enldm xlc[2] mclk[2] gpio0[2] gpio1[2] gpio2[2] dio2 adcref[0] adcoffs[2] adc[2] tstrim[2] tvoffs[2] wtr[2] wtm[10] wtm[2] wtv[10] wtv[2] lbdt[2] vbat[2] encrc Reserved synclen[1] prealen[2] sync[26] sync[18] sync[10] sync[2] txhd[26] txhd[18] txhd[10] txhd[2] pklen[2] adc8[2] enamp2x txpow[2] txdr[10] txdr[2] enmaninv fd[8] fd[2] fo[2] Reserved fb[2] fc[10] fc[2] fhch[2] fhs[2] txafthr[2] txaethr[2] fifod[2] D1 vc[1] cps[1] Reserved ichiprdy Reserved enchiprdy pllon Reserved xlc[1] mclk[1] gpio0[1] gpio1[1] gpio2[1] dio1 adcgain[1] adcoffs[1] adc[1] tstrim[1] tvoffs[1] wtr[1] wtm[9] wtm[1] wtv[9] wtv[1] lbdt[1] vbat[1] crc[1] pktx synclen[0] prealen[1] sync[25] sync[17] sync[9] sync[1] txhd[25] txhd[17] txhd[9] txhd[1] pklen[1] adc8[1] bufovr txpow[1] txdr[9] txdr[1] enmanch modtyp[1] fd[1] fo[1] fo[9] fb[1] fc[9] fc[1] fhch[1] fhs[1] txafthr[1] txaethr[1] fifod[1] D0 vc[0] cps[0] Reserved ipor Reserved enpor xton ffclrtx xlc[0] mclk[0] gpio0[0] gpio1[0] gpio2[0] dio0 adcgain[0] adcoffs[0] adc[0] tstrim[0] tvoffs[0] wtr[0] wtm[8] wtm[0] wtv[8] wtv[0] lbdt[0] vbat[0] crc[0] pksent prealen[8] prealen[0] sync[24] sync[16] sync[8] sync[0] txhd[24] txhd[16] txhd[8] txhd[0] pklen[0] adc8[0] enbuf txpow[0] txdr[8] txdr[0] enwhite modtyp[0] fd[0] fo[0] fo[8] fb[0] fc[8] fc[0] fhch[0] fhs[0] txafthr[0] txaethr[0] fifod[0] POR Default 06h -- -- -- 00h 03h 01h 00h 7Fh 06h 00h 00h 00h 00h 00h 00h -- 20h 00h 03h 00h 01h -- -- 14h -- 8Dh -- 22h 08h 2Dh D4h 00h 00h 00h 00h 00h 00h 00h 10h 24h 18h 0Ah 3Dh 0Ch 00h 20h 00h 00h 75h BBh 80h 00h 00h 37h 04h --
R/W Low Battery Detector Threshold R Battery Voltage Level R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Data Access Control EzMAC status Header Control 2 Preamble Length Sync Word 3 Sync Word 2 Sync Word 1 Sync Word 0 Transmit Header 3 Transmit Header 2 Transmit Header 1 Transmit Header 0 Transmit Packet Length ADC8 Control Crystal Oscillator/Control Test TX Power TX Data Rate 1 TX Data Rate 0 Modulation Mode Control 1 Modulation Mode Control 2 Frequency Deviation Frequency Offset 1 Frequency Offset 2 Frequency Band Select Nominal Carrier Frequency 1 Nominal Carrier Frequency 0 Frequency Hopping Channel Select Frequency Hopping Step Size TX FIFO Control 1 TX FIFO Control 2 FIFO Access
Reserved Reserved adc[5] adc[4] entsoffs entstrim tvoffs[5] tvoffs[4] Reserved wtr[4] wtm[13] wtm[12] wtm[5] wtm[4] wtv[13] wtv[12] wtv[5] wtv[4] Reserved Reserved lbdt[4] 0 vbat[4] Reserved crcdonly Reserved Reserved Reserved Reserved hdlen[1] hdlen[0] prealen[5] prealen[4] sync[29] sync[28] sync[21] sync[20] sync[13] sync[12] sync[5] sync[4] txhd[29] txhd[28] txhd[21] txhd[20] txhd[13] txhd[12] txhd[5] txhd[4] pklen[5] pklen[4] adc8[5] adc8[4] Reserved pwst[0] clkhyst papeaklvl[1] papeaklvl[0] txdr[13] txdr[12] txdr[5] txdr[4] txdtrtscale enphpwdn dtmod[1] dtmod[0] fd[5] fd[4] fo[5] fo[4] Reserved Reserved hbsel fb[4] fc[13] fc[12] fc[5] fc[4] fhch[5] fhch[4] fhs[5] fhs[4] txafthr[5] txafthr[4] txaethr[5] txaethr[4] Reserved fifod[5] fifod[4]
Note: Detailed register descriptions are available in "RFM42B/43B Register Descriptions."
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RFM42B/43B
10. Pin Descriptions: RFM42B/43B RFM42B/43B-S1
RFM42B/43B-S2
RFM42B/43B-D
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RFM42B/43B
VCC GND GPIO_0 GPIO_1 GPIO_2 SDO S S I/O I/O I/O O registers. Serial Data input. 0-VCC V digital input. This pin provides the serial data stream for the 4-line SDI I serial data bus. Serial Clock input. 0-VDD V digital input. This pin provides the serial data clock function for SCLK I the 4-line serial data bus. Data is clocked into the RFM42/43 on positive edge transitions. Serial Interface Select input. 0- VCC V digital input. This pin provides the Select/Enable nSEL I function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. General Microcontroller Interrupt Status output. When the RFM42/43 exhibits anyone of the Interrupt Events the nIRQ pin will be set low=0. Please see the Control Logic registers nIRQ O section for more information on the Interrupt Events. The Microcontroller can then determine the state of the interrupt by reading a corresponding SPI Interrupt Status Registers, Address 03h and 04h. I SDN Shutdown input pin. 0-VCC V digital input. SDN should be = 0 in all modes except Shutdown mode. When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. ANT NC I/O RF signal output/input.(50 OHM output /input Impedance) No Connection +1.8 to +3.6 V supply voltage. The recommended VCC supply voltage is +3.3 V. Ground reference. General Purpose Digital I/O that may be configured through the registers to perform various functions including: Microcontroller Clock Output, FIFO status, POR, Wake-Up timer, Low Battery Detect, TRSW, AntDiversity control, etc. See the SPI GPIO Configuration Registers, Address 0Bh, 0Ch, and 0Dh for more information. 0-VCC V digital output that provides a serial readback function of the internal control
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RFM42B/43B
12. Mechanical Dimension:RFM42B/43B
SMD PACKAGES1
SMD PACKAGES2
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RFM42B/43B
DIP PACKAGED
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RFM42B/43B
13. Ordering Information
Part Number=module type--operation band--package type
RFM42B/43B--433--D
module type
operation band
Package
example1RFM43B module at 433MHz band, DIP : RFM43B-433-D 2RFM42B module at 868MHZ band, SMD, thickness at 4.9mm: RFM42B-868-S1
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RFM42B/43B
This document may contain preliminary information and is subject to change by Hope Microelectronics without notice. Hope Microelectronics assumes no HOPE MICROELECTRONICS CO.,LTD Add:4/F, Tel: Fax: Email: Block B3, East Industrial Area, Huaqiaocheng, Shenzhen, Guangdong, China 86-755-82973805 86-755-82973550 sales@hoperf.com trade@hoperf.com responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Hope Microelectronics or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in the direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A ARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
(c)2006, HOPE MICROELECTRONICS CO.,LTD. All rights reserved.
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